Author: qwell
Date: Wed Oct 17 16:04:51 2007
New Revision: 633
URL:
http://svn.digium.com/view/aadk?view=rev&rev=633
Log:
Merge many of the changes made in the bf537-stamp board.
Modified:
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash-
defines.h
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash.
c
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/post-m
emory.c
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/s800i.
c
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/stm_m2
5p64.c
Modified:
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash-
defines.h
URL: http://svn.digium.com/view/
aadk/u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/f
lash-defines.h?view=diff&rev=633&r1=632&r2=633
============================================================
==================
---
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash-
defines.h (original)
+++
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash-
defines.h Wed Oct 17 16:04:51 2007
 -49,10
+49,6
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
-
-asm("#define FLASH_START_L 0x0000");
-asm("#define FLASH_START_H 0x2000");
-
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
int get_codes(void);
-61,7
+57,7
int erase_flash(void);
int erase_block_flash(int);
void unlock_flash(long lOffset);
-int write_data(long lStart, long lCount, uchar *pnData);
+int write_data(long lStart, long lCount, uchar * pnData);
int read_flash(long nOffset, int *pnValue);
int write_flash(long nOffset, int nValue);
void get_sector_number(long lOffset, int *pnSector);
-70,7
+66,6
int AFP_NumSectors = 71;
long AFP_SectorSize2 = 0x10000;
int AFP_SectorSize1 = 0x2000;
-
#define NUM_SECTORS 71
Modified:
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash.
c
URL: http://svn.digium.com/view/aadk/u-b
oot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash.c?v
iew=diff&rev=633&r1=632&r2=633
============================================================
==================
---
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash.
c (original)
+++
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/flash.
c Wed Oct 17 16:04:51 2007
-27,6
+27,8
*/
#include <malloc.h>
+#include <config.h>
+#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
-34,14
+36,13
reset_flash();
}
-unsigned long flash_get_size(ulong baseaddr, flash_info_t *
info,
- int bank_flag)
+unsigned long flash_get_size(ulong baseaddr, flash_info_t *
info, int bank_flag)
{
int id = 0, i = 0;
static int FlagDev = 1;
id = get_codes();
- if(FlagDev) {
+ if (FlagDev) {
FlagDev = 0;
}
info->flash_id = id;
-50,7
+51,9
for (i = PriFlashABegin; i < SecFlashABegin; i++)
info->start[i] = (baseaddr + (i * AFP_SectorSize1));
for (i = SecFlashABegin; i < NUM_SECTORS; i++)
- info->start[i] = (baseaddr + SecFlashAOff +
((i-SecFlashABegin) * AFP_SectorSize2));
+ info->start[i] =
+ (baseaddr + SecFlashAOff +
+ ((i - SecFlashABegin) * AFP_SectorSize2));
info->size = 0x800000;
info->sector_count = NUM_SECTORS;
break;
-88,12
+91,16
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b ==
0) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx
= %ld MBn",
- size_b, size_b >> 20);
+ size_b, size_b >> 20);
}
/* flash_protect (int flag, ulong from, ulong to,
flash_info_t *info) */
- (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH_BASE,(flash
_info[0].start[2] - 1),&flash_info[0]);
- (void)flash_protect(FLAG_PROTECT_SET, 0x203F0000,
0x203FFFFF, &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
+ (flash_info[0].start[2] - 1), &flash_info[0]);
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+ (void)flash_protect(FLAG_PROTECT_SET, 0x203F0000,
0x203FFFFF,
+ &flash_info[0]);
+#endif
return (size_b);
}
-106,21
+113,21
printf("missing or unknown FLASH typen");
return;
}
-
+
switch (info->flash_id) {
+ case (STM_ID_29W320EB & 0xFFFF):
case (STM_ID_29W320DB & 0xFFFF):
printf("ST Microelectronics ");
break;
default:
- printf("Unknown Vendor ");
+ printf("Unknown Vendor: (0x%08X) ",
info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("n ");
printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : "
");
+ info->start[i], info->protect[i] ? "
(RO)" : " ");
}
printf("n");
return;
-128,50
+135,69
int flash_erase(flash_info_t * info, int s_first, int
s_last)
{
- int cnt = 0,i;
- int prot,sect;
+ int cnt = 0, i;
+ int prot, sect;
prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
if (prot)
- printf ("- Warning: %d protected
sectors will not be erased!n", prot);
- else
- printf ("n");
+ printf("- Warning: %d protected sectors will not be
erased!n",
+ prot);
+ else
+ printf("n");
cnt = s_last - s_first + 1;
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
printf("Erasing Flash locations, Please
Waitn");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
- if(erase_block_flash(i) < 0) {
+ if (erase_block_flash(i) < 0) {
printf("Error Sector erasing n");
return FLASH_FAIL;
}
}
}
- printf ("n");
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ if (cnt == FLASH_TOT_SECT) {
+ printf("Erasing flash, Please Wait n");
+ if (erase_flash() < 0) {
+ printf("Erasing flash failed n");
+ return FLASH_FAIL;
+ }
+ } else {
+ printf("Erasing Flash locations, Please
Waitn");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i) < 0) {
+ printf("Error Sector erasing n");
+ return FLASH_FAIL;
+ }
+ }
+ }
+ }
+#endif
+ printf("n");
return FLASH_SUCCESS;
}
int write_buff(flash_info_t * info, uchar * src, ulong
addr, ulong cnt)
{
int d;
- if(addr%2){
- read_flash(addr-1-CFG_FLASH_BASE,&d);
- d = (int)((d&0x00FF)|(*src++<<8));
- write_data(addr-1,2,&d);
- write_data(addr+1,cnt-1,src);
- }
- else
+ if (addr % 2) {
+ read_flash(addr - 1 - CFG_FLASH_BASE, &d);
+ d = (int)((d & 0x00FF) | (*src++ << 8));
+ write_data(addr - 1, 2, (uchar *) & d);
+ write_data(addr + 1, cnt - 1, src);
+ } else
write_data(addr, cnt, src);
return FLASH_SUCCESS;
}
-
-int write_data(long lStart, long lCount, uchar *pnData)
+int write_data(long lStart, long lCount, uchar * pnData)
{
long i = 0;
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
-179,43
+205,47
int nSector = 0;
int flag = 0;
- if(lCount%2){
- flag = 1;
- lCount = lCount -1;
- }
-
- for(i = 0; i< lCount-1;i+=2,ulOffset+=2){
+ if (lCount % 2) {
+ flag = 1;
+ lCount = lCount - 1;
+ }
+
+ for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
- if(d != 0xffff) {
- printf("Flash not
erased at offset 0x%x Please erase to reprogram
n",ulOffset);
- return FLASH_FAIL;
- }
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%x Please erase
to reprogram n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
unlock_flash(ulOffset);
- d = (int)(pnData[i]|pnData[i+1]<<8);
- write_flash(ulOffset,d);
- if(poll_toggle_bit(ulOffset) < 0){
- printf("Error
programming the flash n");
- return FLASH_FAIL;
- }
- if((i>0)&&(!(i%AFP_SectorSize2)))
- printf(".");
- }
- if(flag){
+ d = (int)(pnData[i] | pnData[i + 1] << 8);
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash n");
+ return FLASH_FAIL;
+ }
+ if ((i > 0) && (!(i % AFP_SectorSize2)))
+ printf(".");
+ }
+ if (flag) {
get_sector_number(ulOffset, &nSector);
- read_flash(ulOffset, &d);
- if(d != 0xffff) {
- printf("Flash not
erased at offset 0x%x Please erase to reprogram
n",ulOffset);
- return FLASH_FAIL;
- }
- unlock_flash(ulOffset);
- d = (int)(pnData[i]|(d&0xFF00));
- write_flash(ulOffset,d);
- if(poll_toggle_bit(ulOffset) < 0){
- printf("Error
programming the flash n");
- return FLASH_FAIL;
- }
- }
+ read_flash(ulOffset, &d);
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%x Please erase
to reprogram n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ d = (int)(pnData[i] | (d & 0xFF00));
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash n");
+ return FLASH_FAIL;
+ }
+ }
return FLASH_SUCCESS;
}
-224,14
+254,19
long addr;
addr = (CFG_FLASH_BASE + nOffset);
- *(unsigned volatile short *) addr = nValue;
- __builtin_bfin_ssync();
+ *(unsigned volatile short *)addr = nValue;
+ sync();
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+ if (icache_status())
+ udelay(CONFIG_CCLK_HZ / 1000000);
+#endif
return FLASH_SUCCESS;
}
int read_flash(long nOffset, int *pnValue)
{
- unsigned short *pFlashAddr = (unsigned short
*)(CFG_FLASH_BASE + nOffset);
+ unsigned short *pFlashAddr =
+ (unsigned short *)(CFG_FLASH_BASE + nOffset);
*pnValue = *pFlashAddr;
-240,28
+275,29
int poll_toggle_bit(long lOffset)
{
- unsigned int u1,u2;
- volatile unsigned long *FB = (volatile unsigned long
*)(CFG_FLASH_BASE + lOffset);
- while(1) {
+ unsigned int u1, u2;
+ volatile unsigned long *FB =
+ (volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
+ while (1) {
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
- u1^= u2;
- if( !(u1 & 0x0040))
+ u1 ^= u2;
+ if (!(u1 & 0x0040))
break;
- if( !(u2 & 0x0020))
+ if (!(u2 & 0x0020))
continue;
- else{
- u1 = *(volatile unsigned short *)FB;
- u2 = *(volatile unsigned short *)FB;
- u1^= u2;
- if( !(u1 & 0x0040))
- break;
- else{
+ else {
+ u1 = *(volatile unsigned short *)FB;
+ u2 = *(volatile unsigned short *)FB;
+ u1 ^= u2;
+ if (!(u1 & 0x0040))
+ break;
+ else {
reset_flash();
return FLASH_FAIL;
- }
}
}
+ }
return FLASH_SUCCESS;
}
-281,7
+317,7
write_flash(WRITESEQ5, WRITEDATA5);
write_flash(WRITESEQ6, WRITEDATA6);
- if(poll_toggle_bit(0x0000) < 0)
+ if (poll_toggle_bit(0x0000) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
-293,17
+329,18
if ((nBlock < 0) || (nBlock > AFP_NumSectors))
return FALSE;
-
- // figure out the offset of the block in flash
- if( (nBlock >=0) && (nBlock
<SecFlashABegin))
+
+ /* figure out the offset of the block in flash */
+ if ((nBlock >= 0) && (nBlock <
SecFlashABegin))
ulSectorOff = nBlock * AFP_SectorSize1;
- else if( (nBlock >= SecFlashABegin) && (nBlock
< NUM_SECTORS) )
- ulSectorOff = SecFlashAOff + (nBlock-SecFlashABegin)*
AFP_SectorSize2;
- // no such sector
+ else if ((nBlock >= SecFlashABegin) && (nBlock
< NUM_SECTORS))
+ ulSectorOff =
+ SecFlashAOff + (nBlock - SecFlashABegin) *
AFP_SectorSize2;
+ /* no such sector */
else
return FLASH_FAIL;
-
+
write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
-312,7
+349,7
write_flash(ulSectorOff, BlockEraseVal);
- if(poll_toggle_bit(ulSectorOff) < 0)
+ if (poll_toggle_bit(ulSectorOff) < 0)
return FLASH_FAIL;
printf(".");
-336,8
+373,6
write_flash(WRITESEQ1, GETCODEDATA1);
write_flash(WRITESEQ2, GETCODEDATA2);
write_flash(WRITESEQ3, GETCODEDATA3);
-
-
read_flash(0x0402, &dev_id);
dev_id &= 0x0000FFFF;
-353,19
+388,16
long lMainEnd = 0x400000;
long lBootEnd = 0x10000;
- // sector numbers for the FLASH A boot sectors
- if(ulOffset < lBootEnd)
- {
- nSector = (int)ulOffset / AFP_SectorSize1 ;
- }
- // sector numbers for the FLASH B boot sectors
- else if( ( ulOffset >= lBootEnd ) && ( ulOffset
< lMainEnd ) )
- {
- nSector = (( ulOffset / (AFP_SectorSize2) ) + 7 );
- }
-
- // if it is a valid sector, set it
- if ( (nSector >= 0) && (nSector <
AFP_NumSectors) )
+ /* sector numbers for the FLASH A boot sectors */
+ if (ulOffset < lBootEnd) {
+ nSector = (int)ulOffset / AFP_SectorSize1;
+ }
+ /* sector numbers for the FLASH B boot sectors */
+ else if ((ulOffset >= lBootEnd) && (ulOffset
< lMainEnd)) {
+ nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
+ }
+ /* if it is a valid sector, set it */
+ if ((nSector >= 0) && (nSector <
AFP_NumSectors))
*pnSector = nSector;
}
Modified:
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/post-m
emory.c
URL: http://svn.digium.com/view/aa
dk/u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/pos
t-memory.c?view=diff&rev=633&r1=632&r2=633
============================================================
==================
---
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/post-m
emory.c (original)
+++
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/post-m
emory.c Wed Oct 17 16:04:51 2007
-1,4
+1,5
#include <common.h>
+#include <asm/io.h>
#ifdef CONFIG_POST
-14,117
+15,119
#define SCLK_NUM 3
void post_out_buff(char *buff);
-int post_key_pressed(void);
+int post_key_pressed(void);
void post_init_pll(int mult, int div);
-int post_init_sdram(int sclk);
+int post_init_sdram(int sclk);
void post_init_uart(int sclk);
const int pll[CCLK_NUM][SCLK_NUM][2] = {
- { {20, 4}, {20, 5}, {20, 10} }, /*
CCLK = 500M */
- { {16, 4}, {16, 5}, {16, 8} }, /*
CCLK = 400M */
- { {8 , 2}, {8, 4}, {8, 5} }, /*
CCLK = 200M */
- { {4 , 1}, {4, 2}, {4, 4} } /*
CCLK = 100M */
- };
+ {{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
+ {{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
+ {{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
+ {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
+};
const char *const log[CCLK_NUM][SCLK_NUM] = {
- {"CCLK-500Mhz SCLK-125Mhz:
Writing... ",
- "CCLK-500Mhz SCLK-100Mhz:
Writing... ",
- "CCLK-500Mhz SCLK- 50Mhz:
Writing... ",},
- {"CCLK-400Mhz SCLK-100Mhz:
Writing... ",
- "CCLK-400Mhz SCLK- 80Mhz:
Writing... ",
- "CCLK-400Mhz SCLK- 50Mhz:
Writing... ",},
- {"CCLK-200Mhz SCLK-100Mhz:
Writing... ",
- "CCLK-200Mhz SCLK- 50Mhz:
Writing... ",
- "CCLK-200Mhz SCLK- 40Mhz:
Writing... ",},
- {"CCLK-100Mhz SCLK-100Mhz:
Writing... ",
- "CCLK-100Mhz SCLK- 50Mhz:
Writing... ",
- "CCLK-100Mhz SCLK- 25Mhz:
Writing... ",},
- };
-
-int memory_post_test (int flags)
+ {"CCLK-500Mhz SCLK-125Mhz: Writing... ",
+ "CCLK-500Mhz SCLK-100Mhz: Writing... ",
+ "CCLK-500Mhz SCLK- 50Mhz: Writing... ",},
+ {"CCLK-400Mhz SCLK-100Mhz: Writing... ",
+ "CCLK-400Mhz SCLK- 80Mhz: Writing... ",
+ "CCLK-400Mhz SCLK- 50Mhz: Writing... ",},
+ {"CCLK-200Mhz SCLK-100Mhz: Writing... ",
+ "CCLK-200Mhz SCLK- 50Mhz: Writing... ",
+ "CCLK-200Mhz SCLK- 40Mhz: Writing... ",},
+ {"CCLK-100Mhz SCLK-100Mhz: Writing... ",
+ "CCLK-100Mhz SCLK- 50Mhz: Writing... ",
+ "CCLK-100Mhz SCLK- 25Mhz: Writing... ",},
+};
+
+int memory_post_test(int flags)
{
int addr;
- int m,n;
+ int m, n;
int sclk, sclk_temp;
int ret = 1;
- sclk_temp = CLKIN/1000000;
+ sclk_temp = CLKIN / 1000000;
sclk_temp = sclk_temp * CONFIG_VCO_MULT;
- for(sclk = 0; sclk_temp>0;sclk++)
+ for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= CONFIG_SCLK_DIV;
sclk = sclk * 1000000;
post_init_uart(sclk);
- if(post_key_pressed() == 0)
+ if (post_key_pressed() == 0)
return 0;
- for(m=0;m<CCLK_NUM; m++){
- for(n=0;n< SCLK_NUM; n++){
- /* Calculate the sclk */
- sclk_temp = CLKIN/1000000;
- sclk_temp = sclk_temp*pll[m][n][0];
- for(sclk=0;sclk_temp>0;sclk++)
+ for (m = 0; m < CCLK_NUM; m++) {
+ for (n = 0; n < SCLK_NUM; n++) {
+ /* Calculate the sclk */
+ sclk_temp = CLKIN / 1000000;
+ sclk_temp = sclk_temp * pll[m][n][0];
+ for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= pll[m][n][1];
sclk = sclk * 1000000;
-
- post_init_pll(pll[m][n][0],pll[m][n][1]);
+
+ post_init_pll(pll[m][n][0], pll[m][n][1]);
post_init_sdram(sclk);
post_init_uart(sclk);
post_out_buff("nr ");
post_out_buff(log[m][n]);
- for(addr=0x0;addr<CFG_MAX_RAM_SIZE;addr+=4)
- *(unsigned long *)addr = PATTERN1;
- post_out_buff("Reading... ");
- for(addr=0x0;addr<CFG_MAX_RAM_SIZE;addr+=4){
- if( (*(unsigned long *)addr)!=
PATTERN1){
+ for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
+ *(unsigned long *)addr = PATTERN1;
+ post_out_buff("Reading... ");
+ for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
{
+ if ((*(unsigned long *)addr) != PATTERN1) {
post_out_buff("Errornr ");
ret = 0;
}
- }
+ }
post_out_buff("OKnr ");
}
}
- if(ret)
+ if (ret)
post_out_buff("memory POST passednr ");
else
post_out_buff("memory POST failednr ");
post_out_buff("nrnr ");
- return 1;
-}
-
-void post_init_uart(int sclk) {
+ return 1;
+}
+
+void post_init_uart(int sclk)
+{
int divisor;
- for(divisor =0;sclk > 0;divisor ++)
- sclk -= 57600*16;
-
+ for (divisor = 0; sclk > 0; divisor++)
+ sclk -= 57600 * 16;
+
*pPORTF_FER = 0x000F;
- *pPORTH_FER = 0xFFFF;
-
- *pUART_GCTL = 0x00;
- *pUART_LCR = 0x83;
- __builtin_bfin_ssync();
- *pUART_DLL = (divisor & 0xFF);
- __builtin_bfin_ssync();
- *pUART_DLH = ((divisor >> 8) & 0xFF);
- __builtin_bfin_ssync();
- *pUART_LCR = 0x03;
- __builtin_bfin_ssync();
- *pUART_GCTL = 0x01;
- __builtin_bfin_ssync();
-}
-
-void post_out_buff (char *buff) {
-
- int i=0;
- for(i=0;i< 0x80000;i++);
+ *pPORTH_FER = 0xFFFF;
+
+ *pUART_GCTL = 0x00;
+ *pUART_LCR = 0x83;
+ sync();
+ *pUART_DLL = (divisor & 0xFF);
+ sync();
+ *pUART_DLH = ((divisor >> 8) & 0xFF);
+ sync();
+ *pUART_LCR = 0x03;
+ sync();
+ *pUART_GCTL = 0x01;
+ sync();
+}
+
+void post_out_buff(char *buff)
+{
+
+ int i = 0;
+ for (i = 0; i < 0x80000; i++) ;
i = 0;
- while ( (buff[i] != ' ') && ( i != 100 ) )
{
- while ( ! (*pUART_LSR & 0x20) ) ;
- *pUART_THR=buff[i];
- __builtin_bfin_ssync();
- i++;
- }
- for(i=0;i< 0x80000;i++);
+ while ((buff[i] != ' ') && (i != 100)) {
+ while (!(*pUART_LSR & 0x20)) ;
+ *pUART_THR = buff[i];
+ sync();
+ i++;
+ }
+ for (i = 0; i < 0x80000; i++) ;
}
/* Using sw10-PF5 as the hotkey */
-132,178
+135,188
#define KEY_DELAY 0x80
int post_key_pressed(void)
{
- int i, n;
+ int i, n;
unsigned short value;
- *pPORTF_FER &= ~PF5;
- *pPORTFIO_DIR &= ~PF5;
- *pPORTFIO_INEN|= PF5;
- __builtin_bfin_ssync();
-
- post_out_buff("########Press SW10 to enter
Memory POST########: 3 ");
- for(i=0;i<KEY_LOOP;i++){
- value = *pPORTFIO & PF5;
- if(*pUART0_RBR == 0x0D){
- value =0;
- goto key_pressed;
- }
- if(value != 0){
- goto key_pressed;
- }
- for(n=0;n<KEY_DELAY;n++);
- }
- post_out_buff("b2 ");
-
- for(i=0;i<KEY_LOOP;i++){
- value = *pPORTFIO & PF5;
- if(*pUART0_RBR == 0x0D){
- value =0;
- goto key_pressed;
- }
- if(value != 0){
- goto key_pressed;
- }
- for(n=0;n<KEY_DELAY;n++);
- }
- post_out_buff("b1 ");
-
- for(i=0;i<KEY_LOOP;i++){
- value = *pPORTFIO & PF5;
- if(*pUART0_RBR == 0x0D){
- value =0;
- goto key_pressed;
- }
- if(value != 0){
- goto key_pressed;
- }
- for(n=0;n<KEY_DELAY;n++);
- }
-key_pressed:
- post_out_buff("b0");
- post_out_buff("nr ");
- if(value == 0)
- return 0;
- post_out_buff("Hotkey has been pressed, Enter
POST . . . . . .nr ");
+ *pPORTF_FER &= ~PF5;
+ *pPORTFIO_DIR &= ~PF5;
+ *pPORTFIO_INEN |= PF5;
+ sync();
+
+ post_out_buff("########Press SW10 to enter Memory
POST########: 3 ");
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ post_out_buff("b2 ");
+
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ post_out_buff("b1 ");
+
+ for (i = 0; i < KEY_LOOP; i++) {
+ value = *pPORTFIO & PF5;
+ if (*pUART0_RBR == 0x0D) {
+ value = 0;
+ goto key_pressed;
+ }
+ if (value != 0) {
+ goto key_pressed;
+ }
+ for (n = 0; n < KEY_DELAY; n++)
+ asm("nop");
+ }
+ key_pressed:
+ post_out_buff("b0");
+ post_out_buff("nr ");
+ if (value == 0)
+ return 0;
+ post_out_buff("Hotkey has been pressed, Enter POST .
. . . . .nr ");
return 1;
}
-void post_init_pll(int mult, int div) {
-
- *pSIC_IWR=0x01;
- *pPLL_CTL=(mult<<9);
- *pPLL_DIV = div;
- asm("CLI R2;");
- asm("IDLE;");
- asm("STI R2;");
- while (! (*pPLL_STAT & 0x20)) ;
-}
-
-int post_init_sdram(int sclk) {
- int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num,
SDRAM_tRCD, SDRAM_tWR;
- int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE,
SDRAM_WIDTH, mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
-
-if (( sclk > 119402985 )) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_7;
- SDRAM_tRAS_num = 7;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 104477612 ) && ( sclk <=
119402985 )) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_6;
- SDRAM_tRAS_num = 6;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 89552239 ) && ( sclk <=
104477612 )) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_5;
- SDRAM_tRAS_num = 5;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 74626866 ) && ( sclk <=
89552239 )) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_4;
- SDRAM_tRAS_num = 4;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 66666667 ) && ( sclk <=
74626866 )) {
- SDRAM_tRP = TRP_2;
- SDRAM_tRP_num = 2;
- SDRAM_tRAS = TRAS_3;
- SDRAM_tRAS_num = 3;
- SDRAM_tRCD = TRCD_2;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 59701493 ) && ( sclk <=
66666667 )) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_4;
- SDRAM_tRAS_num = 4;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 44776119 ) && ( sclk <=
59701493 )) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_3;
- SDRAM_tRAS_num = 3;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
-} else if (( sclk > 29850746 ) && ( sclk <=
44776119 )) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_2;
- SDRAM_tRAS_num = 2;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
-} else if ( sclk <= 29850746 ) {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_1;
- SDRAM_tRAS_num = 1;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
-} else {
- SDRAM_tRP = TRP_1;
- SDRAM_tRP_num = 1;
- SDRAM_tRAS = TRAS_1;
- SDRAM_tRAS_num = 1;
- SDRAM_tRCD = TRCD_1;
- SDRAM_tWR = TWR_2;
-}
+void post_init_pll(int mult, int div)
+{
+
+ *pSIC_IWR = 0x01;
+ *pPLL_CTL = (mult << 9);
+ *pPLL_DIV = div;
+ asm("CLI R2;");
+ asm("IDLE;");
+ asm("STI R2;");
+ while (!(*pPLL_STAT & 0x20)) ;
+}
+
+int post_init_sdram(int sclk)
+{
+ int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num,
SDRAM_tRCD,
+ SDRAM_tWR;
+ int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE,
SDRAM_WIDTH,
+ mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
+
+ if ((sclk > 119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_7;
+ SDRAM_tRAS_num = 7;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 104477612) && (sclk <=
119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_6;
+ SDRAM_tRAS_num = 6;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 89552239) && (sclk <=
104477612)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_5;
+ SDRAM_tRAS_num = 5;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 74626866) && (sclk <=
89552239)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 66666667) && (sclk <=
74626866)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 59701493) && (sclk <=
66666667)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 44776119) && (sclk <=
59701493)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 29850746) && (sclk <=
44776119)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_2;
+ SDRAM_tRAS_num = 2;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if (sclk <= 29850746) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ }
/*SDRAM INFORMATION: */
- SDRAM_Tref = 64; /* Refresh period in milliseconds
*/
- SDRAM_NRA = 4096; /* Number of row addresses in SDRAM
*/
- SDRAM_CL = CL_3; // 2
-
- SDRAM_SIZE = EBSZ_64;
- SDRAM_WIDTH = EBCAW_10;
-
-
- mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
+ SDRAM_Tref = 64; /* Refresh period in milliseconds */
+ SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
+ SDRAM_CL = CL_3; /* 2 */
+
+ SDRAM_SIZE = EBSZ_64;
+ SDRAM_WIDTH = EBCAW_10;
+
+ mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
/* Equation from section 17 (p17-46) of BF533 HRM */
- mem_SDRRC = ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) /
SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num);
+ mem_SDRRC =
+ (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA)
-
+ (SDRAM_tRAS_num + SDRAM_tRP_num);
/* Enable SCLK Out */
- mem_SDGCTL = ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP |
SDRAM_tRCD | SDRAM_tWR | PSS );
-
- __builtin_bfin_ssync();
-
+ mem_SDGCTL =
+ (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP |
SDRAM_tRCD | SDRAM_tWR
+ | PSS);
+
+ sync();
+
*pEBIU_SDGCTL |= 0x1000000;
/* Set the SDRAM Refresh Rate control register based on
SSCLK value */
- *pEBIU_SDRRC = mem_SDRRC;
-
- //SDRAM Memory Bank Control Register
- *pEBIU_SDBCTL= mem_SDBCTL;
-
- //SDRAM Memory Global Control Register
- *pEBIU_SDGCTL= mem_SDGCTL;
- __builtin_bfin_ssync();
+ *pEBIU_SDRRC = mem_SDRRC;
+
+ /* SDRAM Memory Bank Control Register */
+ *pEBIU_SDBCTL = mem_SDBCTL;
+
+ /* SDRAM Memory Global Control Register */
+ *pEBIU_SDGCTL = mem_SDGCTL;
+ sync();
return mem_SDRRC;
}
-#endif /* CONFIG_POST & CFG_POST_MEMORY */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CFG_POST_MEMORY */
+#endif /* CONFIG_POST */
Modified:
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/s800i.
c
URL: http://svn.digium.com/view/aadk/u-b
oot/branches/upstreamsync/u-boot_1.1.6/board/s800i/s800i.c?v
iew=diff&rev=633&r1=632&r2=633
============================================================
==================
---
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/s800i.
c (original)
+++
u-boot/branches/upstreamsync/u-boot_1.1.6/board/s800i/s800i.
c Wed Oct 17 16:04:51 2007
-43,9
+43,9
* to also add booting from SPI, or TWI, but this
function does
* not currently support that.
*/
-int do_bootldr (cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
-{
- ulong addr, entry;
+int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char
*argv[])
+{
+ ulong addr, entry;
ulong *data;
/* Get the address */
-56,79
+56,81
}
/* Check if it is a LDR file */
- data = (ulong *)addr;
- if ( *data == 0xFF800060 || *data == 0xFF800040 || *data
== 0xFF800020 ) {
+ data = (ulong *) addr;
+ if (*data == 0xFF800060 || *data == 0xFF800040 || *data ==
0xFF800020) {
/* We want to boot from FLASH or SDRAM */
entry = _BOOTROM_BOOT_DXE_FLASH;
- printf ("## Booting ldr image at 0x%08lx
...n", addr);
- if (icache_status ())
+ printf("## Booting ldr image at 0x%08lx ...n",
addr);
+ if (icache_status())
icache_disable();
- if (dcache_status ())
- dcache_disable ();
-
- __asm__(
- "R7=%[a];n"
- "P0=%[b];n"
- "JUMP (P0);n"
- :
- : [a] "d" (addr), [b] "a" (entry)
- : "R7", "P0" );
+ if (dcache_status())
+ dcache_disable();
+
+ __asm__("R7=%[a];n"
"P0=%[b];n" "JUMP (P0);n":
+ :[a] "d"(addr),[b] "a"(entry)
+ :"R7", "P0");
} else {
- printf ("## No ldr image at address 0x%08lxn",
addr);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(bootldr,2,0,do_bootldr,
- "bootldr - boot ldr image from memoryn",
- "[addr]n - boot ldr image stored in
memoryn");
+ printf("## No ldr image at address 0x%08lxn",
addr);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
+ "bootldr - boot ldr image from memoryn",
+ "[addr]n - boot ldr image stored in
memoryn");
int checkboard(void)
{
- printf("CPU: ADSP BF537 Rev.: 0.%dn",
*pCHIPID >>28);
+#if (BFIN_CPU == ADSP_BF534)
+ printf("CPU: ADSP BF534 Rev.: 0.%dn",
*pCHIPID >> 28);
+#elif (BFIN_CPU == ADSP_BF536)
+ printf("CPU: ADSP BF536 Rev.: 0.%dn",
*pCHIPID >> 28);
+#else
+ printf("CPU: ADSP BF537 Rev.: 0.%dn",
*pCHIPID >> 28);
+#endif
printf("Board: Digium S800in");
printf(" Support: http://www.di
gium.com/en/supportcenter/n");
return 0;
}
-#ifdef CONFIG_BF537_CF
-
-void cf_outb(unsigned char val, volatile unsigned char*
addr)
-{
- *(addr) = val;
- __builtin_bfin_ssync();
+#if defined(CONFIG_BFIN_IDE)
+
+void cf_outb(unsigned char val, volatile unsigned char
*addr)
+{
+ *(addr) = val;
+ sync();
}
unsigned char cf_inb(volatile unsigned char *addr)
{
- volatile unsigned char c;
-
- c = *(addr);
- __builtin_bfin_ssync();
-
- return c;
+ volatile unsigned char c;
+
+ c = *(addr);
+ sync();
+
+ return c;
}
void cf_insw(unsigned short *sect_buf, unsigned short
*addr, int words)
{
- int i;
-
- for (i = 0;i < words; i++)
- *(sect_buf + i) = *(addr);
- __builtin_bfin_ssync();
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(sect_buf + i) = *(addr);
+ sync();
}
void cf_outsw(unsigned short *addr, unsigned short
*sect_buf, int words)
{
- int i;
-
- for (i = 0;i < words; i++)
- *(addr) = *(sect_buf + i);
- __builtin_bfin_ssync();
-}
-#endif
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(addr) = *(sect_buf + i);
+ sync();
+}
+#endif /* CONFIG_BFIN_IDE */
long int initdram(int board_type)
{
-137,7
+139,7
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
- printf("Serial Port initialized with Baud rate =
%xn",brate);
+ printf("Serial Port initialized with Baud rate =
%xn", brate);
printf("SDRAM attributes:n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS
%d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles
n",
-154,34
+156,49
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
char nid[32];
- unsigned short *pMACaddr = (unsigned short *) 0x203F0000;
-
-#if 0
- if ( getenv("ethaddr") == NULL) {
- sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
- pMACaddr[0] & 0xFF , pMACaddr[0] >> 8,
- pMACaddr[1] & 0xFF , pMACaddr[1] >> 8,
- pMACaddr[2] & 0xFF , pMACaddr[2] >> 8);
- setenv ("ethaddr", nid);
- }
-#endif
-#ifdef CONFIG_BF537_CF
- unsigned short *addr = CF_ATASEL_ENA;
- unsigned short buf=0;
-
- cf_outsw(addr, &buf, 1);
- udelay(5000);
+ unsigned char *pMACaddr = (unsigned char *)0x203F0000;
+ u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+ /* The 0xFF check here is to make sure we don't use the
address
+ * in flash if it's simply been erased (aka all 0xFF
values) */
+ if (getenv("ethaddr") == NULL &&
is_valid_ether_addr(pMACaddr)) {
+ sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+ pMACaddr[0], pMACaddr[1],
+ pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
+ setenv("ethaddr", nid);
+ }
+ if (getenv("ethaddr")) {
+ SetupMacAddr(SrcAddr);
+ }
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
+
+#if defined(CONFIG_BFIN_IDE)
+#if defined(CONFIG_BFIN_TRUE_IDE)
+ /* Enable ATASEL when in True IDE mode */
+ printf("Using CF True IDE Moden");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_CF_IDE)
+ /* Disable ATASEL when we're in Common Memory Mode */
+ printf("Using CF Common Memory Moden");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_HDD_IDE)
+ printf("Using HDD IDE Moden");
+#endif
ide_init();
-#endif
+#endif /* CONFIG_BFIN_IDE */
adm_init();
SetupMacAddr(nid);
set_bootcmd_args(); /* Modify arguments that are passed
to OS */
-
- return 0;
-}
-#endif
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
-203,25
+220,57
#endif
#ifdef CONFIG_POST
+#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
+ return 0;
+}
+#else
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+ int delay = 3;
+ int i;
+ unsigned short value;
+
+ *pPORTF_FER &= ~PF5;
+ *pPORTFIO_DIR &= ~PF5;
+ *pPORTFIO_INEN |= PF5;
+
+ printf("########Press SW10 to enter Memory
POST########: %2d ", delay);
+ while (delay--) {
+ for (i = 0; i < 100; i++) {
+ value = *pPORTFIO & PF5;
+ if (value != 0) {
+ break;
+ }
+ udelay(10000);
+ }
+ printf("bbb%2d ", delay);
+ }
+ printf("bbb 0");
+ printf("n");
+ if (value == 0)
return 0;
-}
+ else {
+ printf("Hotkey has been pressed, Enter POST . . . .
. .n");
+ return 1;
+ }
+}
+#endif
#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store(ulong a)
{
- volatile ulong *save_addr =
- (volatile ulong *)POST_WORD_ADDR;
+ volatile ulong *save_addr = (volatile ulong
*)POST_WORD_ADDR;
*save_addr = a;
}
ulong post_word_load(void)
{
- volatile ulong *save_addr =
- (volatile ulong *)POST_WORD_ADDR;
+ volatile ulong *save_addr = (volatile ulong
*)POST_WORD_ADDR;
return *save_addr;
}
#endif
-235,44
+284,50
#define BLOCK_SIZE 0x10000
#define VERIFY_ADDR 0x2000000
extern int erase_block_flash(int);
-extern int write_data(long lStart, long lCount, uchar
*pnData);
+extern int write_data(long lStart, long lCount, uchar *
pnData);
int flash_post_test(int flags)
{
unsigned short *pbuf, *temp;
- int offset,n,i;
+ int offset, n, i;
int value = 0;
int result = 0;
printf("n");
pbuf = (unsigned short *)VERIFY_ADDR;
temp = pbuf;
- for(n=FLASH_START_POST_BLOCK;n<FLASH_END_POST_BLOCK;n++
){
- offset = (n - 7)*BLOCK_SIZE;
+ for (n = FLASH_START_POST_BLOCK; n <
FLASH_END_POST_BLOCK; n++) {
+ offset = (n - 7) * BLOCK_SIZE;
printf("--------Erase block:%2d..", n);
erase_block_flash(n);
printf("OKr");
printf("--------Program block:%2d...", n);
- write_data(CFG_FLASH_BASE+offset, BLOCK_SIZE, pbuf);
+ write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
printf("OKr");
printf("--------Verify block:%2d...", n);
- for(i=0;i< BLOCK_SIZE;i+=2){
- if( *(unsigned short *)(CFG_FLASH_BASE + offset
+i)!=*temp++){
+ for (i = 0; i < BLOCK_SIZE; i += 2) {
+ if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
+ *temp++) {
value = 1;
result = 1;
}
}
- if(value)
+ if (value)
printf("failedn");
else
- printf("OK %3d%%r",(int)((n+1-FLASH_START_PO
ST_BLOCK)*100/(FLASH_END_POST_BLOCK -
FLASH_START_POST_BLOCK)));
+ printf("OK %3d%%r",
+ (int)(
+ (n + 1 -
+ FLASH_START_POST_BLOCK) *
+ 100 / (FLASH_END_POST_BLOCK -
+ FLASH_START_POST_BLOCK)));
temp = pbuf;
value = 0;
}
- printf("n");
- if(result)
+ printf("n");
+ if (result)
return -1;
else
- return 0;
+ return 0;
}
/****************************************************
-282,33
+337,33
****************************************************/
int led_post_test(int flags)
{
- *pPORTF_FER &= ~(PF6|PF7|PF8|PF9|PF10|PF11);
- *pPORTFIO_DIR |= PF6|PF7|PF8|PF9|PF10|PF11;
- *pPORTFIO_INEN &=
~(PF6|PF7|PF8|PF9|PF10|PF11);
- *pPORTFIO &= ~(PF6|PF7|PF8|PF9|PF10|PF11);
+ *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 |
PF11);
+ *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
+ *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 |
PF11);
+ *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
udelay(1000000);
printf("LED1 on");
- *pPORTFIO |= PF6;
+ *pPORTFIO |= PF6;
udelay(1000000);
printf("bbbbbbb");
printf("LED2 on");
- *pPORTFIO |= PF7;
+ *pPORTFIO |= PF7;
udelay(1000000);
printf("bbbbbbb");
printf("LED3 on");
- *pPORTFIO |= PF8;
- udelay(1000000);
+ *pPORTFIO |= PF8;
+ udelay(1000000);
printf("bbbbbbb");
printf("LED4 on");
- *pPORTFIO |= PF9;
+ *pPORTFIO |= PF9;
udelay(1000000);
printf("bbbbbbb");
printf("LED5 on");
- *pPORTFIO |= PF10;
- udelay(1000000);
+ *pPORTFIO |= PF10;
+ udelay(1000000);
printf("bbbbbbb");
printf("lED6 on");
- *pPORTFIO |= PF11;
+ *pPORTFIO |= PF11;
printf("bbbbbbb ");
return 0;
}
-319,88
+374,88
************************************************/
int button_post_test(int flags)
{
- int i,delay = 5;
- unsigned short value = 0;
+ int i, delay = 5;
+ unsigned short value = 0;
int result = 0;
- *pPORTF_FER &= ~(PF5|PF4|PF3|PF2);
- *pPORTFIO_DIR &= ~(PF5|PF4|PF3|PF2);
- *pPORTFIO_INEN|= (PF5|PF4|PF3|PF2);
-
- printf("n--------Press SW10: %2d
",delay);
- while(delay--){
- for(i=0;i<100;i++){
- value = *pPORTFIO & PF5;
- if(value != 0){
- break;
- }
- udelay(10000);
- }
- printf("bbb%2d ",delay);
- }
- if(value!=0)
+ *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
+ *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
[... 969 lines stripped ...]
_______________________________________________
--Bandwidth and Colocation Provided by http://www.api-digital.c
om--
aadk-commits mailing list
To UNSUBSCRIBE or update options visit:
http://lists.digium.com/mailman/listinfo/aadk-commits
|