mcf5208, sdram and cache

Hi Marc,

>>I've real idea what I'm looking for at this stage.
 Could it be an SDRAM
>>config problem ?
>>If it is why does it work with the cache disabled ?
>
>The cache accesses the SDRAM in bursts, so maybe the
bursts
settings/timings
>are incorrect. You should carefully review both your
SDRAM and SDRAM
>controller's init.
>
>Marc

Thanks for your reply. I'm still drawing a blank on this so
setup a test
to try and see what was happening.  I run a test program in
eprom which
inits the sdram and fills the first 32 bytes with 00 01
02...1f a byte
at a time.
I read it back using byte and also long word accesses and
all is ok.
I then init the cache to be a data cache and read the same
locations
again.  Using byte access I get...
0405060708090A0B0C0D0E0F0C0D0E0F1415161718191A1B1C1D1E1F1C1D
1E1F
long word access gives the same result
If I read 32 bytes starting with an address offset of 4 I
get...
08090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F1C1D1E1FXXXX
XXXX
If I then immediately read with an address offset of 0 I
get...
1011121308090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F1C1D
1E1F

I'm sure the above should be telling me something but I
just don't see it.

Has anyone else seen anything like this before ?  is anyone
use SDR
like me instead of DDR ?

Thanks for your time.

Cheers
Paul






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Hi Paul. Again, it looks like an SDRAM/controller
initialization problem. I
used SDR on a 5280 (flash-less 5282). If you provide your
SDRAM's spec, CPU
clock and init sequence, I'll take a look at it tonight.

Marc


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