mcf5208, sdram and cache

Hi Marc,

Many thanks for your continued input on this problem.
I'd not done any dummy access to SDRAM as I'd not seen any
sample code do
that
even though it is mentioned in the manual.
However, when I did a dummy access the cpu hung at that
point.  Further
tests showed
that any dummy access done before locking the SDMR hung the
cpu, I assume
this
means the controller is different to other Freescale devices
?

The good news is that I've now got everything working ok

There were two problems.  The first problem was one you
found where the
mode should
be 0x32 instead of 0x33.  The final problem was my
initialisation of the
clock PLL.  There is
a problem with the sdram controller when exiting limp mode,
although this
is in the errata
sheet for some reason I failed to spot it - doh !

Thanks again.
Paul





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