1. The ramp time should be 1ms (not 1us, that is almost
certainly too fast).
2. The power supplies do need to be sequenced to avoid
reverse biasing the internal diodes, but the note saying the
power supplies need to track is incorrect. As long as you
get the order right (SDVDD/EVDD before IVDD) the timing
shouldn't matter.
-Michael
> -----Original Message-----
> From: ColdFire lists.wildrice.com
> [mailto:ColdFire lists.wildrice.com] On Behalf Of nop head
> Sent: Friday, July 21, 2006 9:09 AM
> To: Norman Michael-ra6329
> Subject: [ColdFire] Fwd: MCF5375 Supply voltage
sequencing
>
>
> Hello All,
>
> I am a bit confused by the 5375 power sequencing
requirements, the
> datasheet is contradictory.
>
> Section 5.4.3 note 4: "Use 1 ms or slower rise
time for all supplies."
> Section 5.4.3.1: "Use 1 μs or slower rise time
for all supplies." "The
> rise times on the power supplies should be slower than
1 μs to avoid
> turning on the internal ESD protection clamp
diodes."
>
> I can't imagine a 240MHz part having anything with a
1ms time constant
> so I guess 1us is correct?
>
> Section 5.4.3.1: "There is no limit on how long
after EVDD/SDV DD
> powers up before IVDD must powered up."
> Note 2: "IVDD/PLLVDD and EVDD/SDVDD should track
up to 0.9 V, then
> separate for the completion of ramps with EV DD/SD VDD
going to the
> higher external voltages. One way to accomplish this is
to use a low
> drop-out voltage regulator."
>
> I would rather use a switching regulator than an LDO
because its more
> efficient, most of the current being on the 1.5V rail.
It is easy to
> sequence switching regs but not easy to make them
track. The first
> statement implies sequencing is fine but the note below
it recommends
> tracking. Why?
>
> Another aspect that is not clear from the datasheet is
the internal
> reset capability. I am led to believe it has an
internal reset
> circuit. Is this true? In which case which rail does it
monitor and
> what threashold does it apply?
>
> Regards, Chris
>
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