Where are DTR6 and DTRA defined and set?

Greetings,

Using a hardware probe while running an HVM guest, I
examined
the Data TLB to see what TRs Xen had setup. It showed that
DTR0,2,4,6,A were valid. Searching the Xen source code, I
found these defined:

DTR0 = IA64_TR_KERNEL
DTR1 = IA64_TR_PERCPU_DATA
DTR2 = IA64_TR_CURRENT_STACK
DTR3 = IA64_TR_MAPPED_REGS
DTR4 = IA64_TR_SHARED_INFO
DTR5 = IA64_TR_VHPT

But these were not found:
DTR6 = ????
DTRA = ????

Can someone tell me where these DTRs are defined and
what code sets them up?

Thanks,
-Paul Leisy

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Hi.

Hmm, although I haven't ever used hw probe, it looks like
that
those indexes you reported are left shifted by one.
Could you check the manual of your hardware probe?

For VTi guest, Xen surely uses KENREL, PERCPU_DATA,
(CURRENT_STACK if the stack isn't mapped by KERNEL),
MAPPED_REGS and VHPT.
So DTR0, 1, 2, 3, 5 should be valid.
By shifting left them by one, we get 0, 2, 4, 6, A.
Those are which you reported.

thanks,

On Fri, May 30, 2008 at 02:24:29PM -0700, Paul Leisy wrote:
> Greetings,
> 
> Using a hardware probe while running an HVM guest, I
examined
> the Data TLB to see what TRs Xen had setup. It showed
that
> DTR0,2,4,6,A were valid. Searching the Xen source code,
I
> found these defined:
> 
> DTR0 = IA64_TR_KERNEL
> DTR1 = IA64_TR_PERCPU_DATA
> DTR2 = IA64_TR_CURRENT_STACK
> DTR3 = IA64_TR_MAPPED_REGS
> DTR4 = IA64_TR_SHARED_INFO
> DTR5 = IA64_TR_VHPT
> 
> But these were not found:
> DTR6 = ????
> DTRA = ????
> 
> Can someone tell me where these DTRs are defined and
> what code sets them up?
> 
> Thanks,
> -Paul Leisy
> 
> _______________________________________________
> Xen-ia64-devel mailing list
> Xen-ia64-devellists.xensource.com
> http://list
s.xensource.com/xen-ia64-devel
> 

-- 
yamahata

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I guess the LSB 1 bit is used for thread id or something
else.
Does the processor support threading?

On Sat, May 31, 2008 at 12:11:49PM +0900, Isaku Yamahata
wrote:
> Hi.
> 
> Hmm, although I haven't ever used hw probe, it looks
like that
> those indexes you reported are left shifted by one.
> Could you check the manual of your hardware probe?
> 
> For VTi guest, Xen surely uses KENREL, PERCPU_DATA,
> (CURRENT_STACK if the stack isn't mapped by KERNEL),
> MAPPED_REGS and VHPT.
> So DTR0, 1, 2, 3, 5 should be valid.
> By shifting left them by one, we get 0, 2, 4, 6, A.
> Those are which you reported.
> 
> thanks,
> 
> On Fri, May 30, 2008 at 02:24:29PM -0700, Paul Leisy
wrote:
> > Greetings,
> > 
> > Using a hardware probe while running an HVM guest,
I examined
> > the Data TLB to see what TRs Xen had setup. It
showed that
> > DTR0,2,4,6,A were valid. Searching the Xen source
code, I
> > found these defined:
> > 
> > DTR0 = IA64_TR_KERNEL
> > DTR1 = IA64_TR_PERCPU_DATA
> > DTR2 = IA64_TR_CURRENT_STACK
> > DTR3 = IA64_TR_MAPPED_REGS
> > DTR4 = IA64_TR_SHARED_INFO
> > DTR5 = IA64_TR_VHPT
> > 
> > But these were not found:
> > DTR6 = ????
> > DTRA = ????
> > 
> > Can someone tell me where these DTRs are defined
and
> > what code sets them up?
> > 
> > Thanks,
> > -Paul Leisy
> > 
> > _______________________________________________
> > Xen-ia64-devel mailing list
> > Xen-ia64-devellists.xensource.com
> > http://list
s.xensource.com/xen-ia64-devel
> > 
> 

-- 
yamahata

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On Sat, May 31, 2008 at 12:15:44PM +0900, Isaku Yamahata
wrote:
> I guess the LSB 1 bit is used for thread id or
something else.
> Does the processor support threading?

Which processor are you using ?
On montecito, there is no dedicated DTR, they are mixed with
DTC.

Tristan.

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Basically Isaku is correct,
I suppose you are using Montecito, there are two threads per
core.
These two threads share TLB cache.

There is a field "tid" in TLB entry to identify
which thread this TLb
entry belongs to.

Usually 
TLB entry #0 belongs to thread 0
TLB entry #1 belongs to thread 1
TLB entry #2 belongs to thread 0
TLB entry #3 belongs to thread 1
And so on.


- Anthony

Isaku Yamahata wrote:
> I guess the LSB 1 bit is used for thread id or
something else.
> Does the processor support threading?
> 
> On Sat, May 31, 2008 at 12:11:49PM +0900, Isaku
Yamahata wrote:
>> Hi.
>> 
>> Hmm, although I haven't ever used hw probe, it
looks like that
>> those indexes you reported are left shifted by
one.
>> Could you check the manual of your hardware probe?
>> 
>> For VTi guest, Xen surely uses KENREL,
PERCPU_DATA,
>> (CURRENT_STACK if the stack isn't mapped by
KERNEL), MAPPED_REGS and
>> VHPT. So DTR0, 1, 2, 3, 5 should be valid.
>> By shifting left them by one, we get 0, 2, 4, 6,
A.
>> Those are which you reported.
>> 
>> thanks,
>> 
>> On Fri, May 30, 2008 at 02:24:29PM -0700, Paul
Leisy wrote:
>>> Greetings,
>>> 
>>> Using a hardware probe while running an HVM
guest, I examined
>>> the Data TLB to see what TRs Xen had setup. It
showed that
>>> DTR0,2,4,6,A were valid. Searching the Xen
source code, I found
>>> these defined: 
>>> 
>>> DTR0 = IA64_TR_KERNEL
>>> DTR1 = IA64_TR_PERCPU_DATA
>>> DTR2 = IA64_TR_CURRENT_STACK
>>> DTR3 = IA64_TR_MAPPED_REGS
>>> DTR4 = IA64_TR_SHARED_INFO
>>> DTR5 = IA64_TR_VHPT
>>> 
>>> But these were not found:
>>> DTR6 = ????
>>> DTRA = ????
>>> 
>>> Can someone tell me where these DTRs are
defined and
>>> what code sets them up?
>>> 
>>> Thanks,
>>> -Paul Leisy
>>> 
>>>
_______________________________________________
>>> Xen-ia64-devel mailing list
>>> Xen-ia64-devellists.xensource.com
>>> http://list
s.xensource.com/xen-ia64-devel

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