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Thread: Interrupt Handling with Multiple CPUs




Interrupt Handling with Multiple CPUs
user name
2006-10-03 15:12:26
Hi,
       I was looking through the FreeBSD 6.1 release code
and had the
following questions related to interrupt handling:

1. How are the interrupts distributed to multiple CPUs in an
SMP system ? On
i386, from the code it appears that that IRQs are tied to
CPUs using a round
robin mechanism whereby a particular interrupt (for eg UART)
would always be
serviced on a particular CPU. Is the same model followed on
other
architectures ?

2. Is there support for directing the interrupt to any CPU
based on the
current load on each CPU ? or round robin the interrupts
across CPUs ?
    If yes, then what happens in the following scenario:
    A interrupt arrives and the handler needs to sleep since
it needs a
sleep mutex which is owned by some other thread. So it uses
the ithread for
that interrupt source to provide the context for sleeping.
At this time,
another interrupt of the same type arrives.

Thanks in advance,
girish
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Interrupt Handling with Multiple CPUs
user name
2006-10-03 17:48:41
On Tuesday 03 October 2006 11:12, Girish Motwani wrote:
> Hi,
>        I was looking through the FreeBSD 6.1 release
code and had the
> following questions related to interrupt handling:
> 
> 1. How are the interrupts distributed to multiple CPUs
in an SMP system ? On
> i386, from the code it appears that that IRQs are tied
to CPUs using a round
> robin mechanism whereby a particular interrupt (for eg
UART) would always be
> serviced on a particular CPU. Is the same model
followed on other
> architectures ?

Not currently.

> 2. Is there support for directing the interrupt to any
CPU based on the
> current load on each CPU ? or round robin the
interrupts across CPUs ?
>     If yes, then what happens in the following
scenario:
>     A interrupt arrives and the handler needs to sleep
since it needs a
> sleep mutex which is owned by some other thread. So it
uses the ithread for
> that interrupt source to provide the context for
sleeping. At this time,
> another interrupt of the same type arrives.

Well, the interrupt is masked in the PIC until the ithread
has run all the 
handlers, so you won't get further interrupts while the
ithread is blocked on 
a lock in a driver's interrupt handler.

-- 
John Baldwin
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