Add a cputable entry for revision B of the AMCC 440SPe.
When adding
this entry, we need to adjust the entry for 440SP Rev. A so
that it
matches more bits of the PVR, since the 440SPe Rev. B has
PVR
53421891, which would match the old 440SP PVR pattern of
53xxx891.
Signed-off-by: Roland Dreier <rolandd cisco.com>
---
I'm still working on cleaning up the PCI Express changes for
440SPe
Rev. B support but I think we might as well queue this up at
least.
I haven't heard from Matt in a while so maybe you could pick
this up
directly Paul?
Thanks,
Roland
diff --git a/arch/powerpc/kernel/cputable.c
b/arch/powerpc/kernel/cputable.c
index b742013..869d5fe 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
-1123,8
+1123,8 static struct cpu_spec cpu_specs[] = {
.platform = "ppc440",
},
{ /* 440SP Rev. A */
- .pvr_mask = 0xff000fff,
- .pvr_value = 0x53000891,
+ .pvr_mask = 0xfff00fff,
+ .pvr_value = 0x53200891,
.cpu_name = "440SP Rev. A",
.cpu_features = CPU_FTRS_44X,
.cpu_user_features = COMMON_USER_BOOKE,
-1133,8
+1133,8 static struct cpu_spec cpu_specs[] = {
.platform = "ppc440",
},
{ /* 440SPe Rev. A */
- .pvr_mask = 0xff000fff,
- .pvr_value = 0x53000890,
+ .pvr_mask = 0xfff00fff,
+ .pvr_value = 0x53400890,
.cpu_name = "440SPe Rev. A",
.cpu_features = CPU_FTRS_44X,
.cpu_user_features = COMMON_USER_BOOKE,
-1142,6
+1142,16 static struct cpu_spec cpu_specs[] = {
.dcache_bsize = 32,
.platform = "ppc440",
},
+ { /* 440SPe Rev. B */
+ .pvr_mask = 0xfff00fff,
+ .pvr_value = 0x53400891,
+ .cpu_name = "440SPe Rev. B",
+ .cpu_features = CPU_FTRS_44X,
+ .cpu_user_features = COMMON_USER_BOOKE,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .platform = "ppc440",
+ },
#endif /* CONFIG_44x */
#ifdef CONFIG_FSL_BOOKE
{ /* e200z5 */
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