iteration thru makefile reloading

(reincluding the list, comments inline)

On 12/26/06, Kevin Route <kevin.routegooglemail.com> wrote:
>
>
> On 12/25/06, Ken Smith <kgsmithgmail.com> wrote:
> > On 12/25/06, Kevin Route <kevin.routegooglemail.com> wrote:
> > > I am trying to create a makefile that will
auto-discover dependencies by
> > > using what I call "iteration thru
makefile reloading" (no recursive
> make).
> >
> > I played with your makefile for a bit and, after
watching it do what I
> > think its trying to do, I'm puzzled as to why you
choose this
> > approach?
>
>  Well, like you suspect it, my concern is not about the
c0 to c5 files, I
> only added this
>  $(shell ....) in oder to have a "self
sufficient" makefile.... and I didn't
> want this to interfere with
>  the dependency graph......
> >   During my investigation, I came up with this
> > reimplementation that superficially does something
like your original.
[clip]
>  Ok, I will try....
>

>  These old c (config) files contain "dependency
information" I try to get
> (automatically) into my "new" make system.
>
>  for example:
>     package-X,version-R
>  contains
>    needed := package-Y,version-S  package-Z,version-T

Ok, lets take these files for granted but make them in a
separate demo file.

---BEGIN prep.mk---
$(shell 
  echo "needed := p2,v1" > 'c1,v1'; 
  echo "needed := p3,v1 p4,v1" > 'c2,v1'; 
  echo "needed := p4,v1" > 'c3,v1'; 
  echo "needed := " > 'c4,v1' ; 
 )
---END prep.mk---

If each file contains a list of dependencies and the
variable they
each declare is called "needed", I still advocate
$(foreach) over
automatic reinvocation of make.

---BEGIN GNUmakefile---
$(foreach inc,$(wildcard c*), 
  $(warning processing dependency file $(inc)) 
  $(eval include $(inc)) 
  $(foreach dep,$(needed), 
    $(warning $(inc) needs $(dep)) 
   ) 
 )
---END GNUmakefile---


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