On Wed, 2008-02-20 at 11:55 -0800, EricDeb wrote:
> Is there a feature in GNU Make that will let me compile
several source
> files with a single command implicitly? I understand I
could write
> rules like this:
>
> a.o b.o c.o d.o : a.c b.c c.c d.c
> $(CC) -c $(CPPFLAGS) $?
You definitely DON'T want to do this. This does completely
the wrong
thing, and will fail badly if you ever try to run parallel
builds (at
least).
> But, this causes a few problems. First, if any of the
.o's are missing
> we'll compile all four sources. Second it will be
tedious to create
> the makefiles like this, especially since this project
has many many
> files in it.
Unfortunately GNU make doesn't have any ability to define
multiple
targets being built from a single invocation of a rule when
creating
explicit rules like this.
Even if it did, what you want is slightly different because
that
behavior would assume that ALL the targets would be built
from a single
invocation.
The only way you can do this is with a sentinel file, like
this:
.sentinel: a.c b.c c.c d.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $?
touch $
a.o b.o c.o d.o: .sentinel
Unfortunately there are still holes in this: for example if
someone
deletes a .o file then this won't rebuild anything; you'd
have to
explicitly delete the .sentinel file by hand.
There may be ways to work around this as well, but it would
require some
fancier footwork.
--
------------------------------------------------------------
-----------------
Paul D. Smith <psmith gnu.org>
http://make.mad-scientis
t.us
"Please remain calm--I may be mad, but I am a
professional."--Mad Scientist
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