Vad,
On Tue, Mar 25, 2008 at 1:54 AM, Vad N <vadimid gmail.com> wrote:
> depend : main.c
> $(CC) -M $(CPPFLAGS) $^ > $
>
> include depend
> ------------------
>
> I type in command line:
>
> >>make -f myMakefile
> cc -M main.c > depend
> make: 'depend' is up to date.
>
> I assumed that above make produce main.o, but it did.
why?
Make only builds the first target specified in the Makefile,
unless
you provide a command line target. Try this, for example,
with your
Makefile:
$ make main.o
This will build main.o because you specified it as your
desired
target. Otherwise make will only build depend because it's
the first
target in the Makefile. If you want to have main.o be the
primary
target, move your include statement above the rule for
building it:
include depend
depend : main.c
$(CC) -M $(CPPFLAGS) $^ > $
$ make
Makefile:6: depend: No such file or directory
cc -M main.c > depend
cc -c -o main.o main.c
This has the unfortunate side-effect of generating a warning
that
there's no such file as depend, but it doesn't matter
because GNU make
is smart enough to re-run itself on the same Makefile
_after_
generating the file from specified rules, so all your
targets get
built. To remove this warning, you can add a dash to the
front of the
include line:
-include depend
depend : main.c
$(CC) -M $(CPPFLAGS) $^ > $
This causes make to ignore the fact that depend can't be
found on the
first pass. The first pass will build depend, then the
second pass
will work fine because depend is now there.
Regards,
John
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