export variables to sub-make

I'm reading the section 5.7.2 (Communicating Variables to a
Sub-make) and,
unless I missed something, I'm getting behavior I don't
understand.  I
have
a variable that I want to export to a sub-make.  In the
top-level
makefile, it gets assigned a value using "override VAR
+= value" (the base
value is
set from the command line).  When the sub-make is invoked,
only the
original
value is passed, and does not include the value from the +=
statement.

Why is this and how can I fix it?

The Makefile looks like:

=======================================
override VAR += extra
export VAR

all:
   echo $(VAR)
   $(MAKE) -C dir
=======================================

and the second-level file is just:

=======================================
all:
   echo $(VAR)
=======================================

and I invoke this with "make VAR=value".

Thanks,

  Michael


     
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On Wed, 2008-04-30 at 10:52 -0700, Michael Morrell wrote:
> I'm reading the section 5.7.2 (Communicating Variables
to a Sub-make) and,
> unless I missed something, I'm getting behavior I don't
understand.  I
> have a variable that I want to export to a sub-make. 
In the top-level
> makefile, it gets assigned a value using "override
VAR += value" (the base
> value is set from the command line).  When the sub-make
is invoked, only the
> original value is passed, and does not include the
value from the += statement.
> 
> Why is this and how can I fix it?

It's because command line variable settings are passed on
the command
line to submakes as well, and they're passed in EXACTLY the
way they
were passed into the parent make.

So, when you run "make VAR=value", then the
submake is invoked with
exactly the same arguments: "make VAR=value".

That means that values that come into the submake from the
environment
(as from "export var" in the parent make) will
still be environment
variable settings, and will be overridden by the command
line values.

> =======================================
> override VAR += extra
> export VAR
> all:
>    echo $(VAR)
>    $(MAKE) -C dir
> =======================================
> 
> =======================================
> all:
>    echo $(VAR)
> =======================================

To make this work I guess you'll have to change the
"all" rule in the
parent make to do something like this:

	all:
		$(MAKE) -C dir VAR=$(VAR)

-- 
------------------------------------------------------------
-----------------
 Paul D. Smith <psmithgnu.org>                
http://make.mad-scientis
t.us
 "Please remain calm--I may be mad, but I am a
professional."--Mad Scientist




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