Automatic variables

I have a Makefile with several rules:

dir/1/file_1.bdfi : $(shell deps file_1.bdf) | dir/1
	command file_1.bdf > dir/1/file_1.bdfi

dir/2/file_2.bdfi : $(shell deps file_2.bdf) | dir/2
	command file_2.bdf > dir/2/file_2.bdfi

dir/3/file_3.bdfi : $(shell deps file_3.bdf) | dir/3
	command file_3.bdf > dir/3/file_3.bdfi

Is there a way of reducing these to 1 rule with automatic
variables? I
have tried things like:

%.bdfi : $(shell deps $(basename $(F)).bdf) | $(D)
	command $(basename $(F)).bdf > $

and

dir/%/file_%.bdfi : $(shell deps file_%.bdf) | dir/%
	command $(basename $(F)).bdf > $

but the automatic variable don't seem to work in the
dependencies.

Please CC me on replies, as I am not subscribed.

Regards

Jeff


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>>>>> "Jeffrey" == Jeffrey
Ratcliffe <jeffrey.ratcliffegmail.com> writes:

Jeffrey> I have a Makefile with several rules:
Jeffrey> dir/1/file_1.bdfi : $(shell deps file_1.bdf) |
dir/1
Jeffrey> 	command file_1.bdf > dir/1/file_1.bdfi
[...]

Jeffrey> Is there a way of reducing these to 1 rule with
automatic
Jeffrey> variables?
Jeffrey> %.bdfi : $(shell deps $(basename $(F)).bdf)
| $(D)
Jeffrey> 	command $(basename $(F)).bdf > $

For this kind of thing you need secondary expansion.
See the node "Secondary Expansion" in the GNU Make
manual.

Tom


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2008/5/6 Tom Tromey <tromeyredhat.com>:
> >>>>> "Jeffrey" == Jeffrey
Ratcliffe <jeffrey.ratcliffegmail.com> writes:
>
>  Jeffrey> I have a Makefile with several rules:
>  Jeffrey> dir/1/file_1.bdfi : $(shell deps
file_1.bdf) | dir/1
>  Jeffrey>        command file_1.bdf >
dir/1/file_1.bdfi
>  [...]
>
>  Jeffrey> Is there a way of reducing these to 1 rule
with automatic
>  Jeffrey> variables?
>  Jeffrey> %.bdfi : $(shell deps $(basename $(F)).bdf)
| $(D)
>  Jeffrey>        command $(basename $(F)).bdf
> $
>
>  For this kind of thing you need secondary expansion.
>  See the node "Secondary Expansion" in the
GNU Make manual.

Thanks for the tip. I tried

.SECONDEXPANSION
%.bdfi : $$(shell deps $$(*F).bdf) | $$(D)
       command $(*F).bdf > $

but I get "make: *** No rule to make target"
errors, seemingly because
$$(*F).bdf isn't expanded as expected. Is there anyway of
getting make
to print the prerequisites for a particular pattern? In the
--debug=A
output, the correct pattern is tried, but discarded.

Please CC me on replies, as I am not subscribed.

Regards

Jeff


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