Abbreviating dependencies in pattern rules and generalizing rules

Hello,
	I'm trying to write a series of makefiles with reduced
logic to ease  
maintenance on the LTP group. I'm still a bit green in this
game, so  
please bear with me...
	I am trying to write a series of pattern based targets,
like the  
following:

%.o: %.c $(TARGETS)

	However, the dependency list is getting overwritten by the
implicit  
rule shown below.

%.o: %.c
	$(COMPILE.c) $(OUTPUT_OPTION) $< -o $

	Which is understandable, given the nature of the rule.
However, is  
there a shorter / more comprehensible way to write the rule
instead of  
the following?

%.o: %.c $(TARGETS)
	$(CC) $(CFLAGS) $(LDFLAGS) (ever other flag var you could
dream of  
goes here...) $(LOADLIBES) $< -o $

	On a similar note as well, would the best means to
construct a  
simple, generic set of implicit patterns for a series of
Makefiles be  
with a define, similar to this fashion?

define SOME_RULE

TOP	= $

OBJS	= $(pathsubst %.c,%.o,$(wildcard *.c))

OBJS	= $(filter-out $(OBJS))

all: $(TOP)

$(TOP): $^

clean:
	$(RM) $(TOP) $^

install:
	$(INSTALL) $(TOP) /path/to/blah

endif

Thanks!
-Garrett


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