Help about "Include" in Makefile

I have write a makefile like this:

OBJS = $(patsubst %.cpp ,%.o,$(CPP))
DEPS = $(patsubst %.cpp ,%.d,$(CPP))

all : $(OBJS) $(DEPS)

%.o : %.cpp
...

%.d : %.cpp
...

-include $(DEPS)

clean:
    rm -f $(OBJS)
    rm -f $(DEPS)

we do make it will first generate the depend files (.d
files);

but when i do make clean, it also generate depend file
before doing
clean. what can i do to avoid this uncessary

operation!

Hello,

* blippman wrote on Wed, Jun 27, 2007 at 09:15:48AM CEST:
> I have write a makefile like this:
> 
> OBJS = $(patsubst %.cpp ,%.o,$(CPP))
> DEPS = $(patsubst %.cpp ,%.d,$(CPP))
> 
> all : $(OBJS) $(DEPS)

> ...
> %.d : %.cpp
> ...
> 
> -include $(DEPS)
> 
> clean:
>     rm -f $(OBJS)
>     rm -f $(DEPS)
> 
> we do make it will first generate the depend files (.d
files);
> 
> but when i do make clean, it also generate depend file
before doing
> clean. what can i do to avoid this uncessary
operation!

Well, you could use Automake to compute your dependencies,
or a similar
technique to the one Automake uses.  It generates at the end
of
configure a set of stub dependency files.

Cheers,
Ralf