Well, bugger it all to heck.
It appears that 32-bit immediates are *sign*-extended in
64-bit mode,
rather than zero-extended, as moving into registers are
(sheesh, are we
confused yet?)
In other words,
mov rax,dword foo ; 48 C7 C0 xx xx xx xx
mov eax,foo ; B8 xx xx xx xx
... will produce different values if bit 31 of foo is set.
I'm still inclined to have "mov rax,foo" produce
the 64-bit form by
default, but it might make a stronger cause for having the
optimizer
handle relaxation of this form.
mov rax,foo ; 48 B8 xx xx xx xx xx xx xx xx
Depending on the value of "foo", this 10-byte
instruction can be
converted to either a 5- or a 7-byte form.
I do want to know if this makes people have other opinions.
Anyone
happens to know what MASM does about this?
-hpa
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