List Info

Thread: SA1100 register state information




SA1100 register state information
user name
2006-03-25 13:09:56
Hi

While debugging my IPAQ 3100, I found strange that the
kernel report
(DC|IC|WB) register disabled:

cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
cpu0: DC disabled IC disabled WB disabled EABT

It seems that the cpu code is never told of the state of
those register.
The attached patch correct it:

cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
cpu0: DC enabled IC enabled WB enabled LABT

It's a pure cosmetical change, but it could be useful when
debugging 

Arnaud

--- /usr/src/sys/arch/arm/arm/cpufunc.c	2005-12-27
01:19:09.000000000 +0100
+++ arm/arm/cpufunc.c	2006-02-09 19:32:24.000000000 +0100
 -2178,6
+2178,7 
 	cpu_idcache_wbinv_all();
 
 	/* Set the control register */    
+	curcpu()->ci_ctrl = cpuctrl;
 	cpu_control(0xffffffff, cpuctrl);
 }
 #endif	/* CPU_SA1100 || CPU_SA1110 */
SA1100 register state information
user name
2006-03-25 15:26:08
On Sat, Mar 25, 2006 at 02:09:56PM +0100, Arnaud LACOMBE
wrote:
> Hi
> 
> While debugging my IPAQ 3100, I found strange that the
kernel report
> (DC|IC|WB) register disabled:
> 
> cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
> cpu0: DC disabled IC disabled WB disabled EABT
> 
> It seems that the cpu code is never told of the state
of those register.
> The attached patch correct it:
> 
> cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
> cpu0: DC enabled IC enabled WB enabled LABT
> 
> It's a pure cosmetical change, but it could be useful
when debugging 
> 

Looks ok to me.
I'll commit this tomorrow unless anyone objects.

-- 
Peter Postma
SA1100 register state information
user name
2006-09-04 19:36:48
On Sat, Mar 25, 2006 at 04:26:08PM +0100, Peter Postma
wrote:
> On Sat, Mar 25, 2006 at 02:09:56PM +0100, Arnaud
LACOMBE wrote:
> > Hi
> > 
> > While debugging my IPAQ 3100, I found strange that
the kernel report
> > (DC|IC|WB) register disabled:
> > 
> > cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
> > cpu0: DC disabled IC disabled WB disabled EABT
> > 
> > It seems that the cpu code is never told of the
state of those register.
> > The attached patch correct it:
> > 
> > cpu0 at mainbus0: SA-1110 step B-4 (SA-1 core)
> > cpu0: DC enabled IC enabled WB enabled LABT
> > 
> > It's a pure cosmetical change, but it could be
useful when debugging 
> > 
> 
> Looks ok to me.
> I'll commit this tomorrow unless anyone objects.

Eeek. It smells like this it what was confusing me when I
tried to port to
the Jornada 820. Hope I'll find some time to try again
soon.

	-is
[1-3]

about | contact  Other archives ( Real Estate discussion Medical topics )