Re: yamt-idlelwp fallout for mips/cobalt?

Byron.ServiesSun.COM wrote:

> > (I'm not sure if cobalt firmware clears BSS when
> >  it loads a kernel directly without our native
bootloader)
 :
> I don't see anything that looks like clearing bss,

With some quick tests on my RaQ2, the firmware doesn't
seem to clear BSS region of a loaded kernel and
memset() call against BSS is required in kernel itself.

Anyway I'll commit the following change if there is no
objection.
(some other mips ports may need the similar fix)
---
Izumi Tsutsui


Index: cobalt/machdep.c
============================================================
=======
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/machdep.c,v
retrieving revision 1.82
diff -u -r1.82 machdep.c
--- cobalt/machdep.c	17 May 2007 14:51:16 -0000	1.82
+++ cobalt/machdep.c	23 May 2007 09:50:20 -0000
 -174,7
+174,7 
 #endif
 
 	/*
-	 * Clear the BSS segment.
+	 * Clear the BSS segment (if needed).
 	 */
 #if NKSYMS || defined(DDB) || defined(LKM)
 	if (memcmp(((Elf_Ehdr *)end)->e_ident, ELFMAG, SELFMAG)
== 0 &&
 -182,12
+182,33 
 		esym = end;
 		esym += ((Elf_Ehdr *)end)->e_entry;
 		kernend = (char *)mips_round_page(esym);
+		/*
+		 * We don't have to clear BSS here
+		 * since our bootloader already does it.
+		 */
+#if 0
 		memset(edata, 0, end - edata);
+#endif
 	} else
 #endif
 	{
 		kernend = (void *)mips_round_page(end);
+		/*
+		 * No symbol table, so assume we are loaded by
+		 * the firmware directly with "bfd" command.
+		 * The firmware loader doesn't clear BSS of
+		 * a loaded kernel, so do it here.
+		 */
 		memset(edata, 0, kernend - edata);
+
+		/*
+		 * XXX
+		 * lwp0 and cpu_info_store are allocated in BSS
+		 * and initialized before mach_init() is called,
+		 * so restore them again.
+		 */
+		lwp0.l_cpu = &cpu_info_store;
+		cpu_info_store.ci_curlwp = &lwp0;
 	}
 
 	/* Check for valid bootinfo passed from bootstrap */

On Wed, May 23, 2007 at 06:54:13PM +0900, Izumi Tsutsui
wrote:

> Anyway I'll commit the following change if there is no
objection.
> (some other mips ports may need the similar fix)

..

> +		/*
> +		 * XXX
> +		 * lwp0 and cpu_info_store are allocated in BSS
> +		 * and initialized before mach_init() is called,
> +		 * so restore them again.
> +		 */
> +		lwp0.l_cpu = &cpu_info_store;
> +		cpu_info_store.ci_curlwp = &lwp0;

Can you try forcing them into the data segment and see if
that works? Eg:

struct cpu_info cpu_info_store = { .ci_curlwp = &lwp0
};
lwp_t lwp0 = { .l_stat = LSONPROC };

I think cpu_info_store should live somewhere else, like
mips_machdep.c.
I can have a look once I have 'net connectivity again.

Andrew